The present invention relates to a semiconductor storage device and, more particularly, to a technique for realizing high-speed operation and low latency in the semiconductor storage device.
A semiconductor storage device can perform high-speed operation since it electrically records data by using semiconductor elements. In such a semiconductor storage device, there is a case where a DLL (Delay Locked Loop) circuit for adjusting timing of a clock signal is provided.
Patent document 1 describes a technique of providing a delay fixed loop assuring operation margin which allows generation of a rising/polling out enable signal by a clock signal whose timing is adjusted by a DLL circuit even when the frequency of an input clock becomes high, and realizing increased operation frequency of a DRAM (Dynamic Random Access Memory).
Patent document 2 also describes a DLL circuit. The DLL circuit includes a delay clock signal output signal and a data latch circuit. The delay clock signal output circuit outputs a reference clock signal delayed by time specified in accordance with a phase shift between a reference clock signal which is input to an input terminal and a delayed reference clock signal which is fed back from a tail end of a clock tree. In the case where delay time of the reference clock signal which is output from the delay clock signal output circuit is changed, the data latch circuit operates only for a predetermined period.